In a typical process employed in the design of a modern integrated circuit, designers first specify an overall operation to be achieved by an integrated circuit. The specified operation is defined at a high level of abstraction and generally describes a desired set of operations to be performed by of the integrated circuit. Once specified, the overall operation of the integrated is then successively broken into components and sub-components with each component or sub-component performing a specific operation or set of operations. After the overall operation has been broken down into its lowest level of operational components and/or sub-components, a model of the integrated circuit design is then constructed by assembling and interconnecting functional modules, each of which possesses a low level of functionality. These functional modules, otherwise known as leaf modules, are defined for the integrated circuit design and perform functions such as arithmetic functions, AND functions, OR functions, and various other functions. The leaf modules typically are defined by inputs, outputs, and logical relationships between inputs and outputs and correspond to particular implementations of gates or cells in an actual integrated circuit. After the functional modules are assembled and interconnected to complete the behavioral level model, the leaf modules operating in combination perform the previously specified operation of the integrated circuit design.
The assembled leaf modules and their interconnections provides a behavioral level model of an integrated circuit. The behavioral level model is then used to construct a register transfer level (RTL), a next lower functional level model of the integrated circuit design. The RTL model of the integrated circuit design may then be used to construct a gate level model, a next lower functional level, and then a component level model of the integrated circuit design, still a lower functional level model. The component level model may then be employed to create a physical design file that represents a physical model of the integrated circuit. The physical design file may then be used to generate mask sets used in the manufacture of the integrated circuit design to create a working integrated circuit. Thus, by successively converting the behavioral model of the integrated circuit design to lower and lower functional level, the behavioral model may be used to produce a working integrated circuit.
The creation of behavioral level models is a difficult and tedious process. In typical prior art technique for creating a behavioral level model, leaf modules were manually selected, assembled, and interconnected. Because the manual process was overwhelming, the task was often broken into parts wherein implementations of differing operational segments of the overall integrated circuit design were accomplished by different design groups. Once behavioral models were created for each segment, the separate segments were joined into a complete behavioral model by defining interconnections between the functional modules of differing segments of the integrated circuit design. Once assembled, the interconnected segments became a behavioral model of the complete integrated circuit design. The manual process, of course, was prone to error due to the size and complexity of the task. Further, because different design groups worked semi-independently, the segregation of efforts also introduced errors into the behavioral level model.
One particular difficulty arising through the manual assembly and interconnection process related to naming conventions. In almost all integrated circuit designs, some leaf module are used many times. However, because each of the leaf modules had inputs and outputs with common names, difficulties often arose because of duplicate naming problems. Further, when editing the behavioral level model after compilation, edits to inputs and outputs of particular leaf modules having common names could not easily be performed.
Difficulties also often arose in the common naming of differing interconnections within the behavioral level model. These difficulties were most pronounced when separate groups constructed different portions of a behavioral level model. When the behavioral level model included commonly named interconnections that were operationally distinct, the interconnections could be inadvertently connected in a lower functional level implementation of the integrated circuit design based upon the behavioral level model.
Errors in the design of integrated circuits, such as those introduced in assembling and interconnecting leaf modules, are difficult to detect and often are present in the integrated circuits created using the design. Fixing these errors in the actual integrated circuit introduces additional costs and delays. Thus, it is extremely important to reduce or alleviate errors in the design at the time the design is completed.
In many situations, it is desirable to take a proven existing design, to segregate the existing design into a number of functional subparts, to modify the design by adding, removing, or altering functional subparts, and to manufacture other integrated circuits based upon the altered design. Typically, in the reuse of designs, an integrated circuit has been manufactured and completely debugged and has an accurate representation at a component level or gate level, the gate level model being one functional level above the component level and one functional level below the register transfer level. However, it is difficult or impossible to significantly alter a component level or gate level representation of an integrated circuit. Alterations of this scope may only be easily performed within a behavioral level model. Therefore, without a debugged behavioral level model based upon an existing design to modify, it is difficult to reuse and significantly alter a debugged and proven design to create other designs.
Thus there is a need in the art for a technique and system that creates a hierarchical interconnection description of an integrated circuit design, that uses the hierarchical interconnection description in the modification of designs, and that uses the hierarchical interconnection description to translate designs from a lower functional level to a higher functional level.